1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Art
In recent years, there have been known semiconductor devices having a DRAM region in which a DRAM (Dynamic Random Access Memory) is formed, and a logic region in which a CMOS (Complementary Metal Oxide Semiconductor) and so forth are formed, embedded together.
Japanese Laid-Open Patent Publication No. 2005-116582 describes a non-volatile memory cell containing a MONOS transistor for storing data and a MIS transistor for selecting the memory cell, configured so as to have a nitrogen doped region, while being aligned with the gate electrode of the MONOS transistor. According to the configuration, leakage current of the MONOS transistor may reportedly be reduced.
Japanese Laid-Open Patent Publication No. 2001-127270 describes a DRAM-embedded semiconductor device having a DRAM section and a logic section formed on a single substrate, configured to have a silicide layer formed in the surficial portion of each of impurity-diffused regions, both in the logic section and the DRAM section. Formation of the silicide layers in the surficial portions of the impurity-diffused regions raises an effect of reducing contact resistance.
The present inventor has recognized as follows. Formation of the silicide layers in the surficial portions of the impurity-diffused regions raises a problem in that the leakage current may flow between the silicide layers and the substrate unless the impurity-diffused layers are formed to a sufficient depth, and thereby the data retention characteristics of DRAM may degrade.
FIGS. 6A and 6B are drawings schematically illustrating a configuration of an impurity-diffused layer of a transistor. FIG. 6A is a plan view illustrating a gate and an impurity-diffused layer, and FIG. 6B is a sectional view taken along line A-A′ in FIG. 6A. As illustrated in FIG. 6B, a silicide layer may be varied in the thickness, in the process of formation thereof. Variations in the thickness of the silicide layer may be causative of leakage current between a portion of the silicide layer having a large depth, and the substrate. Since the amount of leakage is determined by the minimum distance between the silicide layer and the junction, so that an insufficient depth of the impurity-diffused layer, and consequently shortened distance between the silicide layers and the junction, may increase the amount of leakage, and may degrade data retention characteristics.
On the other hand, the junction is required to be shallowest as possible in the logic region, in order to shorten the gate length of the transistors. Accordingly, it has been demanded that the impurity-diffused layer is formed deeper in the DRAM region, and shallower in the logic region.